In recent electronic devices, various types of technology have been implemented in an attempt to reduce the sizes of the electronic devices, and packaging method for attaching an integrated circuit (IC) to a printed circuit board has also been variously changed. Meanwhile, similar to existing IC packaging techniques such as a ball grid array (BGA), a wafer level chip-scale package (WLCSP), or the like, a circuit having a three-dimensional structure in a package-on-package (POP) form in order to reduce a size of an overall circuit has been used.
Current POP technology uses a relatively complicated method of forming holes in a mold using laser drilling in a general BGA substrate, or the like, and connecting the substrate to an upper circuit using solders, or the like. The complexity results in reduced yield and there is a risk that new investment will occur. In addition, it is difficult to effectively transfer heat generated by the upper circuit stacked on the substrate to the substrate. The inefficient heat transfer result in insufficient temperature, thereby limiting the types of IC that may be stacked. Efficiency at the time of an operation is also reduced.